The present invention relates to the design of integrated circuits (ICs), and more specifically, to placement analysis of such circuits.
In VLSI (very large scale integration) digital design, a netlist (from logic synthesis) includes a network of combinational logic gates and memory elements such as latches/flip-flops. During the placement phase, the netlist is presented as sea-of-standard cells (nodes) with connectivity matrix (edges) for placement during physical design. The placement stage determines the location of cells with the objective to optimize wire length while spreading cells to resolve overlaps and meet density constraints. Current large-scale placement approaches use floating point-based analytical/mathematical techniques to solve a closed form model of Half-Perimeter Wire length (HPWL) as an estimate for routed wire length.
Current floating point approaches are computationally intensive.